Performance evaluation based on the cost criterion of test systems using pipelined control code generators.

Performance evaluation based on the cost criterion of test systems using pipelined control code generators.

Ratnikov M.O. (MAI, Moscow, Russia)

Abstract

This paper is devoted to evaluating the development effort required for designing test systems based on pipelined control code generators and to assessing the effectiveness of using such test systems for selecting fault-tolerance mechanisms in FPGA-based systems from the standpoint of overall project effort. To estimate development effort, the COCOMO II model is proposed, with its coefficients adapted for HDL code. The paper presents an example implementation of three different fault-tolerance approaches within a developed FPGA-based system. The development effort for creating a fault-tolerant system was evaluated for two design routes. In the first route, three versions of the target fault-tolerant system were implemented, and the best one was selected according to predefined criteria. In the second route, before developing the protected target system, an additional analysis was performed using a test system based on a pipelined control code generator. During this analysis, the optimal fault-tolerance method was identified according to specified characteristics and then implemented in the target system. A comparison of the design effort between these two routes was conducted, leading to a conclusion about the efficiency of using the proposed test-system-based approach for selecting fault-tolerance mechanisms. The efficiency evaluation, in terms of development effort, was based on the number of lines of code in the project and included several consecutive steps: from estimating the code size of the baseline target device (without fault-tolerance mechanisms) and the same device protected by each of the fault-tolerance methods under consideration, to comparing the changes in the effort required for selecting and implementing the fault-tolerance approach, as well as the overall change in total project effort.

Keywords

FPGA; COCOMO; effort estimate; project cost; control code; MD4; fault-tolerance; test system; FPGA testing.

Edition

Proceedings of the Institute for System Programming, vol. 38, issue 3, part 1, 2026, pp. 209-222

ISSN 2220-6426 (Online), ISSN 2079-8156 (Print).

DOI: 10.15514/ISPRAS-2026-38(3)-13

For citation

Ratnikov M.O. Performance evaluation based on the cost criterion of test systems using pipelined control code generators.. Proceedings of the Institute for System Programming, vol. 38, issue 3, part 1, 2026, pp. 209-222 DOI: 10.15514/ISPRAS-2026-38(3)-13.

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